The present invention relates generally to semiconductor fabrication and, more particularly, to methods for preparing semiconductor wafers in which preparation operations are performed on a vertically oriented wafer. The preparation is configured to take place in a single enclosure apparatus.
In the fabrication of semiconductor devices, a variety of wafer preparation operations are performed. By way of example, these wafer preparation operations include cleaning operations and polishing/planarization operations, e.g., chemical mechanical planarization (CMP). One known polishing/planarization technique uses platens with planetary polishing motion. One disadvantage of this technique is that it requires multi-step procedures, which are time-consuming and relatively expensive. Another disadvantage of this technique is that it tends to produce wafers having surfaces that suffer from a relatively high degree of topographic variations.
Another known polishing/planarization technique involves circumferential polishing. In one known circumferential polishing system, a wafer is rotated in a vertical orientation by wafer drive rollers. As the wafer is rotated, a pair of cylindrical polishing pads is brought into contact with the opposing surfaces of the wafer. The polishing pads are mounted on counter-rotating mandrels disposed on opposite sides of the wafer being processed. The mandrels span across the diameter of the wafer so as to pass over the wafer center. The rotation of the mandrels causes a rotary pad motion perpendicular to the wafer diameter in a circumferential direction. During the polishing operation, nozzles direct sprays of liquid, e.g., an abrasive slurry, a chemical solution, or a rinse solution, on the opposing surfaces of the wafer.
One drawback of this known circumferential polishing system is that it provides only circumferential polishing motion. As such, the relative velocity of each pad is not uniform across each wafer surface, with the velocity near the wafer edge being greater than the velocity near the wafer center. This is problematic because it not only results in the creation of circumferential residual scratches on each of wafer surfaces, but also results in a more wafer material being removed from the center portion of the wafer than near the perimeter due to the greater dwell time experienced by the center portion of the wafer. As a consequence of this nonuniform material removal rate, each of the opposing surfaces of the wafer tends to have a flared contour, i.e., a contour in which the central portion is depressed relative to the edge portions. As the semiconductor industry moves toward the use of smaller, e.g., 0.18 xcexcm and smaller, feature sizes, such flared contours are undesirable.
In view of the foregoing, there is a need for a method and apparatus for circumferential wafer preparation that minimizes the creation of circumferential residual scratches, provides processed wafers have desired surface contours, and enables multiple wafer preparation operations to be performed on a wafer without moving the wafer between stations.
Broadly speaking, the present invention fills this need by providing methods for preparing wafers.
In accordance with one aspect of the present invention, a method for preparing a semiconductor wafer is provided. The method includes disposing a pair of wafer preparation assemblies in an opposing relationship in an enclosure. Each of the wafer preparation assemblies having a first wafer preparation member and a second wafer preparation member. The method includes disposing a semiconductor wafer between the wafer preparation assemblies in a vertical orientation and rotating the wafer. The method also includes orienting the wafer preparation assemblies such that the first wafer preparation members contact opposing surfaces of the rotating wafer in an opposing relationship and orienting the wafer preparation assemblies such that the second wafer preparation members contact opposing surfaces of the rotating wafer in an opposing relationship.
In accordance with another aspect of the present invention, a method for preparing a semiconductor wafer is provided. The method includes disposing a semiconductor wafer in a vertical orientation in an enclosure. A first wafer preparation operation is performed on the wafer in the enclosure using a first pair of wafer preparation members, and then a second wafer preparation operation is performed on the wafer in the enclosure using a second pair of wafer preparation members.
In yet another aspect of the invention, a method for polishing a semiconductor wafer is provided. This method includes disposing a semiconductor wafer in a vertical orientation in an enclosure and rotating the wafer. A first polishing operation is performed on the rotating wafer in the enclosure using a first pair of cylindrical polishing pads, and then a second polishing operation is performed on the rotating wafer in the enclosure using a second pair of cylindrical polishing pads.
The advantages of the present invention are many and substantial. Most notably, the ability to perform two separate preparation operations in a single enclosure removes the need to move a wafer to multiple stations to accomplish a desired preparation recipe. Also, the less a wafer needs to be transported between modules, the less likelihood it will be that the wafer will be exposed to contaminants or particulates in the transfer.
It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.